Topic: Short Takes: CXL in High Performance Computing; and the UCIe
Standard for Chip Design
Speaker: Kurt Keville, Shankar Viswanathan
Location: Online: https://meet.jit.si/blu.org
Live stream: https://youtube.com/live/DTcRPqLabxc?feature=share
Summary:
New developments in HPC and Chip Design, and various projects from
the 2023 Student Cluster Competition
Abstract:
There are new hardware processes and programming paradigms that promise
to dramatically improve process yields and performance. CXL will unlock
academic research computing disciplines that currently have no solution
path. These include deeply recursive codes and
applications that require large memory blocks.
Unified Acceleration (UXL), was announced last month at the Linux
Foundation Open Source Summit with the goal of delivering a
multi-architecture and multi-vendor software ecosystem for all
accelerators based on open source standards. And Universal Chiplet
Interconnect Express (UCIe) is helping to build an open ecosystem of
chiplets for on-package
innovations.
Bio:
Shankar Viswanathan is the lead performance architect for AMD's
Strategic Silicon products. He has worked on the design and verification
of several generations of AMD processors. Most recently, he was on the
design team for the SoCs that power game consoles such as the
PlayStation5 and the Steam Deck. His general interests like at the
intersection of performance and security in hardware platforms.
Attachments:
HPC Challenge Awards Competition at SC16: https://hpcchallenge.org/
CXL Forum @ HPC + AI on Wall Street:
https://www.hpcaiwallstreet.com/cxl-forum/
1. Student Cluster Competition 2023
<https://www.studentclustercompetition.us/>:
https://www.studentclustercompetition.us/
For further information and directions please consult the BLU Web site:
http://www.blu.org
--
Jerry Feldman<gaf.linux@gmail.com>
Boston Linux and Unixhttp://www.blu.org
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